Device Features

Overall Features

8255 Mode 0

The PCI-1757UP emulates one 8255 programmable peripheral interface (PPI) chip in mode 0, but with higher driving capability than a standard 8255 chip. The 8255 chip has 24 programmable I/O lines that are divided into three 8-bit ports. The total 24 DI/O lines from the chip are divided into 3 ports, designated PA, PB and PC. Each port can be programmed as an input or an output port. The I/O pins in port A are designated PA0, PA1... PA7; the pins in port B are designated PB0, PB1... PB7etc. These port names are used both in this manual. In software library port names are defined as 0, 1 and 2 which are mapping PA, PB and PC, respectively.

8255 chip PA PB PC
Hardware Names PA PB PC
Software Mapping Names 0 1 2

Table 1 Ports Naming Specification

The basic functions of 8255 mode 0 include:

Two 8-bit I/O ports - port A (PA) and port B (PB)

Port C is divided into two nibble-wide (4-bit) I/O ports: PC upper and PC lower

Any port can be used for either input or output.

Output status can be read back.

Interrupt Function of the DIO signals

• Two I/O pins (PC0 and PC4) can be used to generate hardware interrupts. User can program the interrupt control register (Base + 32) to select the interrupt sources.

• Interrupt Source Control

The "mode bits" in the interrupt control register determine the allowable sources of signals generating an interrupt.Bit 0 and bit 1 determine the interrupt source, as indicated in following figure.

Table below shows the relationship between an interrupt source and the values in the mode bits.

M1 M0 Description
0 0 Disable interrupt
0 1 Source=PC00
1 0 Source=PC00&PC04
1 1 Disable interrupt